1. Field of the Invention
This invention relates to computer systems. In particular, the invention relates to canonizing registers.
2. Description of Related Art
An out-of-order processor uses register renaming for enhancing performance. Special arithmetic instructions usually reference the corresponding special registers. For example, in a single instruction multiple data (SIMD) floating-point (FP) processor, there are registers specifically designed for SIMD FP instructions. During the execution of SIMD FP instructions, the SIMD FP registers are renamed and are associated with different physical locations. The renaming information or mapping is stored in a table.
A processor may be used in different modes based on the format of the data representation. A processor may have multiple modes based on the instruction set being used. For example, one mode may be the legacy mode and another mode may be a new extended instruction set. When register renaming is used in one mode and not the other, any transition from one mode to the other may lead to loss of renaming information. For example, the Intel processor family has two modes: an Intel Value Engine (iVE) mode and an Intel Architecture (IA) 64-bit mode (IA64). On an instruction set architecture (ISA) transition from iVE to IA64, the mapping tables are reset and the renaming information is lost.
To preserve the SIMD FP registers across the ISA transitions, the renaming information is to be returned to the canonical space. This process is referred to as canonizing.
During the process of canonizing, each SIMD FP register is to be moved from the renamed space to the canonical space. For each SIMD FP register, two accesses are necessary. For eight registers, this results in sixteen instructions being issued, executed, and retired. This causes the length of the ISA transition to be increased, slowing down the transition.
Therefore, there is a need in the technology to provide a simple and efficient method to canonize registers on transition from one mode to another mode.